1. Field of the Invention
The invention relates to data processing systems and more particularly to a method and apparatus for sequencing through multiple instructions utilizing a write-back path which can handle look-ahead prediction failures, direct memory access (DMA) switching and multiple path switching.
2. Description of the Related Art
The above referenced copending application Ser. No. 07/630,499, now U.S. Pat. No. H001291, describes a Reduced Instruction Set Computer (RISC) that is a superscaler pipelined microprocessor wherein multiple functions are performed during each pipeline stage, that is, multiple multicycle operations occur concurrently. The microprocessor includes a memory coprocessor connected to a MEM interface and a register coprocessor connected to a REG interface. The REG interface is connected to the first and second independent read ports and the first independent write port of a register file. The MEM interface is connected to the third and fourth independent read ports and a second independent write port of the register file. An Instruction Sequencer is connected to the REG interface and to the MEM interface.
An Instruction Cache supplies the instruction sequencer with at least three instruction words per clock. The Instruction Sequencer decodes incoming instruction words from the Cache, and issues up to three instructions on the REG interface, the MEM interface and/or the branch logic within the Instruction Sequencer. The instruction sequencer includes means for detecting dependencies between the instructions being issued to thereby prevent collisions between instructions.
A method of operation of a five pipe-stage pipelined microprocessor is taught. During the first pipe stage the Instruction Sequencer accesses said instruction cache and transfers from said I-Cache to said Instruction Sequencer three or four instruction words depending on whether the instruction pointer (IP) points to an even or odd word address.
During a second pipe stage, the Instruction Sequencer decodes instructions and checks, for dependencies between the issuing instructions. It then issues up to three instructions on the three execution portions of the machine, the REG interface, the MEM interface, and the branch logic within the Instruction Sequencer, only the instructions that can be executed. The sources for all the issued operations are read from the register file during the second pipe stage and, the sources for all the issued operations are sent out to the respective units to use.
During a third pipe stage, the results of doing the EU and/or the AGU ALU/LDA operations are returned to the register file which writes the results into the destination registers of the register file.
During the third pipe stage, the address is issued on the external address bus for loads and stores that go off-chip.
During a fourth pipe stage data is placed on the external data bus.
During a fifth pipe stage the bus controller returns the data to the register file.
It is an object of the present invention to provide an instruction sequencer that controls instruction execution by issuing Micro Addresses (UA)s each cycle, decides which instruction should be executed in the next cycle and handles Instruction pointer (IP) bookkeeping by gathering many boundary conditions from other units, makes guesses and then issues an instruction pointer in such a way that a preceding instruction will not see the change and the following instruction will, taking into account instruction pipelining, branch prediction and fail recovery, macro flow instruction lookahead, and other inter-dependent mechanisms.